# Processor Basics

I ran across a post today that begged for a couple of answers.

# The Question

What I don’t understand is why there’s such reluctance towards making the die bigger. I understand the benefits of making the process smaller, but there has to be a limit somewhere, and it would seem easier/more cost effective to just make the die bigger. Who’s idea was it to have this completely arbitrary general die size and attempt to always stuff more transistors onto it?

If you have a 5mm x 5mm die with 500 million 90nm transistors, you can either halve the process size to 45nm to get 1 billion transistors or you could just double the die size to 10mm x 10mm… Aside from heat and power consumption, why wouldn’t that work?

# Answers

Let’s start with the assumptions:

1. Die Size is “completely arbitrary”: false.
2. It would be more cost-effective to make larger dies: false.
3. There is a reluctance to making the die bigger: false.
4. There has to be a limit to transistor feature size: true.
5. It would be easier to make larger dies for a given design: false.
6. Halving the process from 90 nm to 45 nm would double transistor count: false.
7. “Doubling” the die size from 5 mm x 5 mm to 10 mm x 10 mm would double the transistor count: false.
8. The poster understands the benefits of making the process smaller: false.
9. “Someone” decided to make die size consistent: true.

## Die Size is Not Arbitrary

Processors are manufactured by etching features into large wafers measuring approximately 100 nm to 300 mm in diameter. Intel Samsung, and TSMC announced a transition to 450 mm wafers in 2008. The equipment required to work with wafers dominates whether or not it is economically feasible to increase wafer size. As we will see below, decreasing die size reduces waste and improves yield. So manufacturers have significant pressure to reduce die size.

### Constraints on Wafer Size

1. Wafers are circular.
2. Standard wafer size as of 2011 is 300 mm in diameter
3. Wafer Area: 70,686 mm^2 (pi x (300/2 mm)^2)
4. Equipment for etching wafers is expensive (measured in billions of dollars).
5. Standardizing on wafer size allows manufacturers to control costs.

### Constraints on Die Size

1. Processor dies are square.
2. Large dies waste more surface area for a given wafer.
3. 1 Huge Die: A 300 mm wafer can fit a single large die of 45,000 mm.
4. The wafer has 70,685 mm^2 available area, so this results in a waste of 36.3 percent.
5. A 16×16 mm die has 256 mm^2 area.
6. We can fit 240 256-mm^2 dies onto a single 300 mm wafter (4×4 + 4×8 + 4×12 + 12×12).
7. 240 Dies: Requires 61,440 mm^2, which results in a waste of 13.1 percent.

Result: You can approximate a circle more effectively with smaller dies, resulting in fewer wasted materials.

### Yields

1. The analysis above assumes perfect manufacturing. This is not realistic.
2. In the case of the single large die any imperfection will cause the entire chip to fail.
3. Define the probability of a surface defect as 0.01% per mm^2 etched (just for illustrative purposes).

### Single-Die Wafer

Continuing the example above, we etch 45,000 mm^2 to create our monolithic chip. Unfortunately, our error rate in etching dooms us to failure. On average we expect to find 4.5 errors per chip etched and any error results in a wasted chip. This means our etching process will produce chips with a 100 percent failure rate.

1. 45,000 mm^2 x 0.0001 / mm^2 = 4.5 errors per wafer
2. 1 bad die per wafer / 1 die per wafer = 100% failure rate

### 240-Die Wafer

This scenario is much more realistic. For a 256-mm^2 chip we observe an overall failure rate of 2.9% for the same manufacturing hardware. Clearly smaller dies are much more economical. The worst-cast scenario is when each error occurs in a separate die (multiple errors per die are actually better for our chip failure rate). At most 7 dies will fail.

1. 61,440 mm^2 x 0.0001 / mm^2 = 6.1 errors per wafer
2. 7 bad dies per wafer / 240 dies per wafer = 2.9% failure rate

Result: Smaller dies reduce the impact of etching defects, resulting in higher yields.

## Larger Dies Are Not More Economical

For a given wafer size, decreasing die size improves both yield and cost. Increasing die size reduces yield. A manufacturing process with 99.99% reliability will fail to produce a working 45,000 mm^2 chip 100% of the time. The same process will produce working 256-mm^2 chips 97.1% of the time.

## The industry has increased both die and wafer size

1. Die size has been increasing over time.
2. According to Wikipedia, the die size of the Intel 4004 chip was 12 mm^2.
3. The first Pentium was 294 mm^2.
4. Since then it seems Intel has tried to keep die size under 300 mm^2 as a cost-savings measure.
5. Intel and other manufacturers are currently transitioning to 450 mm wafers, but retooling is expensive.
6. The increase in die area between the Pentium and the 4004 was 24-fold.
7. The increase in transistor count between the Pentium and the 4004 was 1,347-fold.
8. Pentium transistor density: 3,100,000 transistors / 294 mm^2 = 10,544 transistors per mm^2
9. 4004 transistor density: 2,300 transistors / 12 mm^2 = 192 transistors per mm^2
10. Increase in transistor density: 10544/192 = 54.9-fold

Result: Overall chip size measured in transistor count, physical size, and transistor density has been increasing since the introduction of the Intel 4004.

## The Limit to CMOS Feature Size is About 5 nm

1. Individual atoms measure in picometers – about 100 to 500 – or 0.1 to 0.5 nm.
2. Individual transistors need at least 10 atoms to function.
3. 10 x 0.5 nm = 5 nm is the minimum feature size for transistors to function
4. Further improvements require a new class of computation device (1+ transistors per atom instead of atoms per transistor)

Result: Without fundamental improvements in design, we will not be able to scale transistors smaller than 5 nm.

# Math Background on Chip Fabrication

## Doubling in 2D

Whenever we work in two dimensions we have to be careful by what we mean when we say “double”. If you double the area of a square, you only increase the length of each side by a factor of about 1.414 (since 1.414 x 1.414 = 1.99396). If instead we double the length of each side, then we are quadrupling the area!

### Doubling Die Dimensions

1. In the example above, we have a mythical CPU with 500e6 transistors packed into a 25 mm^2 area.
2. This results in a 20e6 / mm^2 transistor density.
3. “Doubling” the die size results in an area of 100 mm^2.
4. (20e6 / mm^2) * 100 mm^2 = 2e9
5. Packing transistors at the same density results in a CPU with 2 billion transistors (4x the original).

Result: Doubling die dimensions quadruples transistor count and die area.

### Halving Feature Size

1. In the case of halving the feature size from 90 nm to 45 nm we see a similar effect.
2. Note that feature size is generally not transistor size – but it should be proportional given the same design.
3. 90 nm x 90 nm = 8100 nm^2.
4. 45 nm x 45 nm = 2025 mm^2.
5. Size difference between 90 nm and 45 nm transistors = 8100 / 2025 = 4.
6. 90 nm CPU: 25 mm^2 / (8100 nm^2) = 3e9 elements maximum
7. 45 nm CPU: 25 mm^2 / (2025 mm^2) = 1.2e10 elements maximum
8. The ratio of transistors to the limit imposed by feature size should match.
9. 90 nm CPU: 500e6 / 3e9 = 0.1667 – this is our ratio
10. 45 nm CPU @ 1 billion transistors: 1e9 / 1.2e10 = 0.0833 – this is not our ratio!
11. 45 nm CPU @ 2 billion transistors: 2e9 / 1.2e10 = 0.1667 – matches!

Result: Halving feature size quadruples transistor count for a given die size.

## Sources

1. The Question Source: http://www.overclock.net/general-processor-discussions/802618-nanometer-processor-picometer-processor.html
2. Intel Wafer: http://download.intel.com/pressroom/images/centrino/Wafer_V2.tif
3. Intel Transistor Counts: http://www.intel.com/pressroom/kits/events/moores_law_40th/
4. Chart of Transistor Count: http://download.intel.com/pressroom/images/events/moores_law_40th/Transistor_Count_bar_chart.jpg
5. Wafer Size: http://arstechnica.com/hardware/news/2008/05/intel-samsung-tsmc-to-hold-hands-and-jump-to-new-wafer-size.ars
6. Wikipedia Transistor Count: http://en.wikipedia.org/wiki/Transistor_count
7. CMOS Scale Limit: http://ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F4531469%2F4539996%2F04540004.pdf%3Farnumber%3D4540004&authDecision=-203
8. Atom Length: http://hypertextbook.com/facts/MichaelPhillip.shtml
9. 10-Atom Transistor: http://discovermagazine.com/2009/jan/051
10. Intel i7 Launch Materials: http://www.intel.com/pressroom/archive/releases/2008/20081117comp_sm.htm
11. Core i7 Die Image: http://download.intel.com/pressroom/kits/corei7/images/Nehalem_Die_Shot_3.jpg
12. Transistor Image: http://www.intel.com/newsroom/kits/22nm/gallery/gallery.htm

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